发明名称 MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY CONTROL METHOD
摘要 According to one embodiment, a memory system includes a nonvolatile memory, a memory interface, a storage unit which stores defective memory cell information, and a storage location control unit which creates second data of a second data length longer than a first data length based on an area at a write destination of first data of the first data length, causes the memory interface to write a plurality of second data to the nonvolatile memory, causes the memory interface to read the second data corresponding to the first data instructed to be read from the nonvolatile memory, and restores the first data based on the read second data and the defective memory cell information.
申请公布号 US2016247581(A1) 申请公布日期 2016.08.25
申请号 US201514849145 申请日期 2015.09.09
申请人 Kabushiki Kaisha Toshiba 发明人 SUZUKI Riki;Hida Toshikatsu;Hara Tokumasa;Yoshii Kenichiro;Kouchi Youhei;Yoshida Norikazu
分类号 G11C29/00;G11C16/10;G11C16/26;G11C16/08 主分类号 G11C29/00
代理机构 代理人
主权项 1. A memory system comprising: a nonvolatile memory; a memory interface configured to control reading/writing data from/to the nonvolatile memory; a defective memory cell information storage unit configured to store defective memory cell information of the nonvolatile memory; and a storage location control unit configured to, in response to a write instruction of a plurality of first data to the nonvolatile memory, each of the plurality of first data having a first data length, create second data for each of the first data based on a memory area in which the first data is to be stored and the defective memory cell information, the second data having a second data length longer than the first data length, and cause the memory interface to write a plurality of second data to the nonvolatile memory, and in response to a read instruction of the first data, cause the memory interface to read the second data corresponding to the first data from the nonvolatile memory, and restore the first data based on the read second data and the defective memory cell information.
地址 Minato-ku JP