发明名称 CONTROL CIRCUIT FOR DYNAMIC RAM
摘要 PURPOSE:To specify a faulty RAM and to continuously operate a system by detecting a faulty dynamic RAM element from among plural dynamic RAM elements in the central processing unit of the system with the aid of the output signal of a logic circuit and the detection signal of plural parity check circuits. CONSTITUTION:The parity check of the data is performed for respective plural dynamic RAM elements 11 to 14, and a parity error is detected by these detection signals for parity check, an active state is detected, and a RAM5 for reserve is connected to the data bus for the system instead of the faulty dynamic RAM element by the detection signal of the parity check for the active state. Thus, the faulty active RAM element can be specified by the parity detection signal of the active state, and the system can be continuously used without temporarily terminating the system.
申请公布号 JPH04132094(A) 申请公布日期 1992.05.06
申请号 JP19900251318 申请日期 1990.09.20
申请人 FUJITSU GENERAL LTD 发明人 KAKIMOTO KOJI
分类号 G06F11/22;G11C29/00;G11C29/04;G11C29/56 主分类号 G06F11/22
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