| 摘要 |
PURPOSE:To increase a pull-in speed by finding out a difference between the 1st and 2nd modulo multiplication signal and using the difference signal as a control signal. CONSTITUTION:A digital phase synchronizing loop is constituted of a modulo 2Rn multiplier 14, an adder 15, an LPF 16, an NCO 17, and a modulo 2Rm multiplier 18, and in a synchronous state, nf1=mf2 (mod2R) is attained. Provided that f1 and f2 are the 1st and 2nd frequency values, and since the f2 is set up to a nominal frequency value by M (fixed information), nf1=mf2 is formed so that f2=(n/m)f1 is formed and an objective frequency signal is obtained. Even if the values (m), (n) are large, speed conversion having a conversion ratio n/m can be attained without reducing the equivalent band width of a PLL and the pull-in speed can be increased. |
