发明名称 GATE ARRAY TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To match the logic level of an I/O circuit with the logic level of an inner cell, and improve the freedom of design, by installing a power supply line to an I/O cell and a power supply line to an cell, and making the supply potentials differ from each other. CONSTITUTION:A two-layered ground wiring of a second layer is divided into a ground wiring 10 for an inner cell and a ground wiring 11 for an 10 cell in an I/O circuit region 3a, and formed in the region 3a. The electric potential supplied to an inner cell 1a is made to differ from the electric potential supplied to the I/O circuit region 3a. Thereby the logic level of an inner cell 2a is driven by a higher or lower potential without being restricted by the logic level of an I/O circuit 7. Hence the delay time is eliminated, or current consumption is reduced by low potential driving, and the restriction of circuit constitution is relieved so that the freedom of design can be increased.
申请公布号 JPH04151856(A) 申请公布日期 1992.05.25
申请号 JP19900276056 申请日期 1990.10.15
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 TAKAMORI KAZUO
分类号 H01L21/822;H01L21/82;H01L27/04 主分类号 H01L21/822
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