发明名称 DELAY CIRCUIT
摘要 PURPOSE:To delay the rise and the fall of a logical signal by the time T of a time constant set in a monostable multivibrator by providing an exclusive logical sum circuit, the monostable multivibrator, and a flip flop circuit. CONSTITUTION:A digital signal is inputted to the input terminal of one side of the exclusive logical sum circuit 1, and the output signal of the flip flop circuit 3 is fed back to the input terminal of the other side, and the time T of the time constant set in the monostable multivibrator 2 provides a delay time to the rising point and the falling point of the inputted digital signal, and the digital signal is outputted from the flip flop circuit 3. Accordingly, the monostable multivibrator 2 is excited by the rise and the fall of the input signal, and outputs a fixed time pulse by the time, constant set in this monostable multivibrator 2. Thus, the signal delayed by definite time pulse length for the rise and the fall of the input signal can be obtained as the output.
申请公布号 JPH04156714(A) 申请公布日期 1992.05.29
申请号 JP19900282240 申请日期 1990.10.19
申请人 NEC CORP 发明人 HORI HIDETOSHI
分类号 H03K5/13 主分类号 H03K5/13
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