发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
PURPOSE:To make it unnecessary to use a selector circuit during test operation by providing means for writing the output signal of a programmable logic array for test patterns on a RAM and for reading out to the external the output signal written on the RAM. CONSTITUTION:An LSI 101 has a PLA 121 and the RAM 106 installed therein. The test operation of the PLA 121 is controlled by a test control signal 33. PLA test input patterns are written on the RAM 106. Next the PLA test input patterns are read out from the RAM 106 and latched in a data latch 131. A selector 111 selects one PLA test input pattern. The PLA 121 outputs a PLA output 21 for the PLA test input pattern selected. The PLA output 21 is latched in a data latch 141 and written on the RAM 106. All of the PLA output data stored on the RAM 106 is analyzed and the PLA 121 is tested. |
申请公布号 |
JPH04175676(A) |
申请公布日期 |
1992.06.23 |
申请号 |
JP19900303445 |
申请日期 |
1990.11.08 |
申请人 |
NEC CORP |
发明人 |
FUKUI TAKAHIRO;WABUKA YUTAKA |
分类号 |
G01R31/28;G01R31/3185;G06F11/22 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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