发明名称 COMPLEMENTARY DECODING INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To attain the circuit constitution which has no dependence on the sizes of transistors (TRs) of both drive and load sides and can improve the TR using efficiency, by making use of an unused driving TR to ensure the complementary actuation between the using drive TR and the load TR to an output signal line. CONSTITUTION:The nCH enhancenent type MOSTRs Q1'-Q3' are connected in series for each output signal line, and an end of each MOSTRQ is connected to an earth line. While the other end of each MOSTRQ is connected to a power supply via other pCH enhancement type MOSTRs Q1-Q3 connected with a gate respectively. The junctures between the circuits connected in series and pCH enhancement type MOSTRs are connected to the gates of the pCH enhancement type MOSTR for load. Thus the load capacity driving performance can be improved without increasing the occupied area. In such a structure, it is possible to obtain a decoding circuit which can be easily designed with a ratioless of a regular structure and has the high driving performance with a small occupied area and small DC power consumption.
申请公布号 JPS59231790(A) 申请公布日期 1984.12.26
申请号 JP19830104205 申请日期 1983.06.13
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 FUKAMI KENNOSUKE;KASAI RIYOUTA
分类号 G11C11/417;G11C11/34;G11C11/413;H01L27/10;(IPC1-7):G11C11/34;H01L27/08;G11C8/00 主分类号 G11C11/417
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