发明名称 VOLTAGE PEAK TIME DETECTION CIRCUIT
摘要 PURPOSE:To detect the normal peak time of input signal voltage, by providing a peak holding circuit, the first comparator, the second comparator, an inverter and an EXOR gate. CONSTITUTION:A peak holding circuit 1 stores the peak voltage up to the present point of time of changing input signal voltage Vi and outputs the same as holding voltage Vh. A comparator 3 detects that the magnitude of the difference voltage Vd between the stored peak voltage and the input signal voltage Vi exceeds reference voltage Vr1 to output comparator output voltage V3. A comparator 4 detects that the magnitude of the difference voltage Vd exceeds reference voltage Vr2 higher than the reference voltage Vr1 to output comparator output voltage V4. An inverter 5 resets the stored peak voltage on the basis of the comparator output voltage V4. An EXOR gate 6 makes the comparator output voltage V3 ineffective on the basis of the comparator output voltage V4.
申请公布号 JPS63171371(A) 申请公布日期 1988.07.15
申请号 JP19870002703 申请日期 1987.01.09
申请人 FUJI ELECTRIC CO LTD 发明人 HANIYU YUTAKA
分类号 G01L19/00;G01R19/04 主分类号 G01L19/00
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