发明名称 INTERPOLATION CIRCUIT FOR DEFECTIVE PACKET
摘要 <p>PURPOSE:To interpolate a defective packet without performing the synchronous control of a complicated circuit and input timing by providing a buffer to hold an interpolation packet transiently separately from the buffer to absorb the delay fluctuation of a packet of packet transfer system, and controlling both buffers selectively corresponding to the normal/defective condition of a reception packet. CONSTITUTION:The normality of an input packet from a network is inspected by a header analyzing part 10, and also, the packet is stored in a delay fluctuation absorbing buffer 11 sequentially. Also, when the input packet is normal, the analyzing part 10 outputs output stored in the buffer 11 by controlling a selector 13. Also, when the input packet is defective, the analyzing part 10 controls the selector 13, and selects the output of the buffer 12 for interpolation where the interpolation packet from an output terminal 16 is held transiently, and outputs it to the output terminal 16, thereby, the interpolation of the defective packet can be performed with simple circuit constitution.</p>
申请公布号 JPH01221958(A) 申请公布日期 1989.09.05
申请号 JP19880045762 申请日期 1988.03.01
申请人 OKI ELECTRIC IND CO LTD 发明人 SHIMOKOSHI KIYOSHI;YOSHIKI TOSHIJI
分类号 H04Q11/04 主分类号 H04Q11/04
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