| 摘要 |
PURPOSE:To easily obtain a capacity of an optimum bit buffer by controlling an address number of an up-down counter to control the capacity of the bit buffer. CONSTITUTION:A coincidence pulse signal 109 representing it that a timewise phase of a signal 105 to apply serial/parallel conversion to a reception signal from one digital transmission communication line and to latch the result and that of a signal 106 to send the signal subjected to parallel/serial conversion after parallel conversion to other digital transmission communication line are coincident, and a reference pulse signal 108 generated at a predetermined time interval are inputted to an R-S flip-flop circuit 10. When the signal 109 is not generated for one period of the signal 108, the capacity of the bit buffer is reduced by one bit, and when the signal 109 is generated for twice or over, the capacity of the bit buffer is increased by one bit. Thus, the optimum capacity of the bit buffer is easily obtained. |
