Vertikaler MOS-Transistor und Verfahren zu dessen Herstellung

摘要

The invention concerns a vertical MOS transistor which comprises a vertical mesa-shaped layer sequence with a drain layer (14), channel layer (15) and source layer (16). The gate dielectric (112) and gate electrode (113') are disposed laterally. Disposed on the opposite side is a dielectric structure (119). The distance between the gate dielectric (112) and dielectric structure (119) is dimensioned such that the MOS transistor is completely depleted. The MOS transistor is produced by self-aligning process steps.