Power supply clamp circuitry for electrostatic discharge (ESD) protection

摘要

Circuitry is provided which increases the efficiency of electrostatic discharge (ESD) power supply clamping circuitry to sink larger currents during an ESD event on a power supply node. Voltage clamp circuits capable of providing ESD protection to a supply node are described. The voltage clamp circuits include a discharge transistor which is controlled by a control circuit during an ESD event. The control circuit operates in response to a voltage provided on the protected supply node. One embodiment provides a P-channel MOS transistor and a control circuit which drives the gate of the transistor. Another embodiment provides an N-channel MOS transistor and a control circuit which drives the gate of the transistor.