| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To suppress reading access delay to occur by parasitic capacitance between bit lines. <P>SOLUTION: In the case of reading, for example, a memory cell 11-11 in which data "0" is stored, the memory cell 11-11 is selected by making a word line WLn into an "H" level and making an NMOS 12-1 into an on state by a signal Yn at the "H" level. In the memory cell 11-11, a drain is reduced to a GND level via the NMOS 12-1 and potential difference occurs between a source and the drain, however, no channel is formed and no current flows. However, a node A is drawn to the GND level by a coupling effect by the parasitic capacitance 14 and charging current i1 flows to the node A since the parasitic capacitance 14 exists between bit lines BL11 and BL21. Along with this, DC current i2 flows from the node A to a GND via an NMOS 22c. Thus, a charging starting period to the parasitic capacitance 14 becomes earlier and reading delay timeΔt is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
