| 摘要 |
<p>A pipelined analog to digital converter comprises a first ADC stage that receives one of an input voltage and a first residue voltage and a first voltage reference and that generates a first digital signal and a second residue voltage. A second ADC stage receives the second residue voltage from the first ADC stage and a second voltage reference and that generates a second digital signal, wherein the second voltage reference is lower than the first voltage reference.</p> |
