STRESS LINER FOR INTEGRATED CIRCUITS

摘要

In one embodiment, a self-aligned contact (SAC) trench structure (412) is formed through a dielectric layer (410) to expose an active region (404) of a MOS transistor. The SAC trench structure (412) not only exposes the active region (404) for electrical connection but also removes portions of a stress liner (409) over the active region (404). This leaves the stress liner (409) mostly on the sidewall and top of the gate (510) of the MOS transistor. Removing portions of the stress liner (409) over the active region substantially removes the lateral component of the strain imparted by the stress liner (409) on the substrate (402), allowing for improved drive current without substantially degrading a complementary MOS transistor.