发明名称 |
Resistive memory device and method of operating the same to reduce leakage current |
摘要 |
A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line. |
申请公布号 |
US9361974(B2) |
申请公布日期 |
2016.06.07 |
申请号 |
US201514683269 |
申请日期 |
2015.04.10 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Lee Yong-Kyu;Byeon Dae-Seok;Lee Yeong-Taek;Yoon Chi-Weon;Park Hyun-Kook;Kwon Hyo-Jin |
分类号 |
G11C11/00;G11C13/00 |
主分类号 |
G11C11/00 |
代理机构 |
Volentine & Whitt, PLLC |
代理人 |
Volentine & Whitt, PLLC |
主权项 |
1. A method of operating a memory device comprising a plurality of memory cells arranged on regions where a plurality of first signal lines and a plurality of second signal lines cross each other, the method comprising:
determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among the plurality of first signal lines; dividing a memory cell array comprising the plurality of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to the unselected second signal lines included in the n blocks, wherein each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line. |
地址 |
Suwon-si, Gyeonggi-do KR |