LOGIC SIMULATION METHOD, LOGIC SIMULATION APPARATUS AND COMPUTER-READABLE STORAGE MEDIUM STORING LOGIC SIMULATION PROGRAM

摘要

A processor detects a phase difference between a feedback clock and a reference clock of a PLL circuit, generates, based on the phase difference, first frequency information indicating a candidate value of a frequency of an output clock being output from the PLL circuit, generates second frequency information by smoothing the first frequency information, and generates the output clock by determining the frequency based on the second

主权项

1. A logic simulation method comprising:
detecting, by a processor, a phase difference between a feedback clock and a reference clock of a PLL circuit including a frequency dividing circuit with a variable frequency dividing ratio; generating, by the processor, first frequency information indicating a candidate value of frequency of an output clock being output from the PLL circuit, based on the phase difference; generating, by the processor, second frequency information by smoothing the first frequency information; and generating, by the processor, the output clock by determining the frequency based on the second frequency information.