发明名称 |
Optical transceiver and method with channel binding, clock forwarding, and integrate-and-dump receivers |
摘要 |
An optical transceiver includes N transmitters each transmitting one of N transmitted optically bound channels; a clock forwarding mechanism to transmit a transmitted optical clock signal to an opposing optical receiver; N receivers each receiving one of N received optically bound channels; and a clock recovery mechanism to receive a received optical clock signal from the opposing optical transmitter. A method and photonically integrated system are also disclosed. The optical transceiver, method, and system optimize system design of WDM highly parallelized transceivers with optical bound channels, a simplified clocking architecture, and boosted receiver sensitivity. The optical transceiver, method, and system include clock recovery followed by data recovery and can utilize integrate-and-dump optical receivers with a recovered clock. |
申请公布号 |
US9413520(B2) |
申请公布日期 |
2016.08.09 |
申请号 |
US201314104534 |
申请日期 |
2013.12.12 |
申请人 |
Ciena Corporation |
发明人 |
Pelekhaty Vladimir;Frankel Michael Y. |
分类号 |
H04J14/02;H04B10/40;H04J7/00;H04L25/14;H04L7/00 |
主分类号 |
H04J14/02 |
代理机构 |
Clements Bernard PLLC |
代理人 |
Clements Bernard PLLC ;Bernard Christopher L.;Baratta, Jr. Lawrence A. |
主权项 |
1. An optical transceiver, comprising:
N transmitters each transmitting one of N transmitted optically bound channels using intensity modulation; a clock forwarding mechanism to transmit a transmitted optical clock signal to an opposing optical receiver; N receivers each receiving one of N received optically bound channels; and a clock recovery mechanism to receive a received optical clock signal from the opposing optical transmitter; wherein the N receivers comprise integrate-and-dump optical receivers that utilize an integration time of about 75% of a bit period providing sufficient time for sampling a value of integrated current and resetting an integrator by discharging an integrating capacitor during the remaining about 25% of the bit period. |
地址 |
Hanover MD US |