Apparatus and method for clock synchronization for inter-die synchronized data transfer

摘要

Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.

主权项

1. A processor comprising:
a pair of interconnects; a first die including:
a first phase interpolator having an output coupled to one of the interconnects; anda delay estimator coupled to the pair of interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.