| 发明名称 | Synapse array, pulse shaper circuit and neuromorphic system | ||
| 摘要 | A synapse array based on a static random access memory (SRAM), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits. At least one synapse circuit among the plurality of synapse circuits includes at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor. | ||
| 申请公布号 | US9418333(B2) | 申请公布日期 | 2016.08.16 |
| 申请号 | US201414165392 | 申请日期 | 2014.01.27 |
| 申请人 | Samsung Electronics Co., Ltd.;Postech Academy-Industry Foundation | 发明人 | Kim Jun Seok;Sim Jae Yoon;Ryu Hyun Surk;Cho Hwasuk |
| 分类号 | G06F15/18;G06N3/08;G06N3/063;G06N3/04;G11C11/412 | 主分类号 | G06F15/18 |
| 代理机构 | NSIP Law | 代理人 | NSIP Law |
| 主权项 | 1. A synapse array based on a static random access memory (SRAM), the synapse array comprising a plurality of synapse circuits, wherein at least one synapse circuit among the plurality of synapse circuits comprises at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor. | ||
| 地址 | Suwon-si KR | ||