Clock circuit and method of operating the same

摘要

A clock gating circuit includes a first transistor, a first inverter and a second transistor. A first terminal of the first transistor receives a clock input signal. A second terminal of the first transistor is coupled to a first node. The first transistor adjusts a voltage of the first node to a first voltage based on the clock input signal. The first inverter is coupled to the first node and receives the voltage of the first node, and outputs a clock output signal. A first terminal of the second transistor receives the clock input signal. A second terminal of the second transistor is coupled to the first node and a second node. The second transistor adjusts the voltage of the first node or the second node to the second voltage, based on the clock input signal.

主权项

1. A clock circuit comprising:
a first transistor having a first terminal and a second terminal, the first terminal of the first transistor configured to receive a clock input signal, the second terminal of the first transistor coupled to a first node, and the first transistor configured to adjust a voltage of the first node to a first voltage level based on the clock input signal; a first inverter coupled to the first node, the first inverter configured to receive the voltage of the first node, and the first inverter being configured to output a clock output signal; and a second transistor having a first terminal and a second terminal, the first terminal of the second transistor configured to receive the clock input signal, the second terminal of the second transistor coupled to the first node and a second node, and the second transistor configured to adjust the voltage of the first node or a voltage of the second node to a second voltage level based on the clock input signal.