| 摘要 |
PURPOSE:To establish lane synchronization at a high speed by checking whether or not all adjacent signal string pairs are a complementary code pairs and specifying the location of the signal string pair being the complementary code pair. CONSTITUTION:The synchronizing circuit is provided with exclusive OR circuits 451-454 checking the C-bit rule as to all adjacent signal strings among output signal strings of a shift matrix 44. Moreover, AND circuits 111-113 setting priority to a positive output of each exclusive OR circuit, pulse width generating circuits 121-123 outputting a pulse signal having a pulse width by 1-3 clock periods in response to an output of each AND circuit and an OR circuit 13 ORing outputs of the pulse width generating circuits and using the result as an input to an AND circuit 49 are provided. Then the presence of the establishment of the C-bit rule of adjacent signal string pairs is checked for all combinations, then a shift stage number from the location of the signal string pair in which the C-bit rule is established till the synchronization position is detected. |
