| 摘要 |
1,029,938. Telegraphy. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 7, 1963 [Oct. 15, 1962], No. 39368/63. Heading H4P. An apparatus for connection between a line and a processor is used (1) to receive characters in synchronous or start-stop serial code and pass them in parallel synchronous code to the processor, or (2) to receive from the processor parallel synchronous or start-stop signals and pass them to line in serial form. These four modes of operation all use a shift register and include means for storing a signal indicating the length of the character currently being operated on. A control word derived from a memory provides an 11-bit word, a 4-bit word used for pre-setting a counter, a 4-bit word indicating the character length, and a 2-bit tag word which determines the mode of operation. Mode 1, synchronous serial data from line 5. The control word sets counter 3 and the 12 stages of shift register 1 to zero. The tag word is fed to register 19, whereby mode signals SR = 0, YS = 1 are derived. The character length is set on register 2 as a binary number and fed to matrix 24 which gives an output on one of 11 leads, whereby one of the entry gates 7 is enacted. The received serial data therefore passes through this gate to the corresponding stage of shift register 1, a bit being transferred at each time t1. At t2 the bits in register 1 are shifted to the right. At t3, counter 3 steps by one. This operation continues until, when the first bit received has reached stage R1, counter 3 shows the same count as does register 2, whereupon comparator 4 pulses. Thus, at t 4, gate 44 enables exit gates 8. Certain of these gates 8 are masked, however, by an arrangement of AND gates 25 and OR gates 26, so that the only gates passing bits in parallel from register 1 to the processor correspond in number to the character length. The comparator output resets counter 3 to zero so that the next character can be received. Mode 2, start-stop serial data from line 5. The various registers are set as described for mode 1. Now, when the first-recieved bit, the Start bit, reaches stage R1 the Stop bit will be in register 58. When these two bits are detected by unit 14 a pulse is given on SS so that, at t3, the Start bit is shifted out of register 1 and is lost. At t4, all the exit gates 8 (the masking gates being inoperative) pass the contents of register 1 to the processor in parallel. Mode 3, parallel synchronous data from the processor received on line 6, and Mode 4, parallel Start-Stop data from the processor. The operation is substantially similar in both modes. As in modes 1 and 2, the control word sets the various registers. At times t1, the bits of the word in the register 1 are read out serially to line, and when comparator 4 pulses a character is passed via gates 9 at t4, in parallel form, to register 1. This character is then read out, as before, from stage R1 of the register, bits being shifted down the register at times t2.
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