| 摘要 |
PURPOSE:To freely set the phase of an output signal in a counter circuit which generates a required timing signal by frequency-dividing an input signal. CONSTITUTION:A frequency division circuit 13 is comprised of four D flip-flop circuits 14-17, and outputs a signal inputted to an input terminal 11 by performing quadripartite frequency division. A decoder 19 outputs a phase signal based on phase data outputted from a phase setting data generating part 18. A comparator 20 compares the combination of the output signals of the flip-flop circuits 14-17 inputted to the input terminals at one side of EXOR gates 21-24 with that of the phase signal outputted from the decoder 19, and outputs a signal of phase in accordance with the phase data outputted from the phase setting data generating part 18. |
