| 摘要 |
<p>PURPOSE:To offer a semiconductor memory with high reliability by preventing an erroneous erasure to a nonvolatile memory transistor on a non-selective ward line during an erasing operation control timing. CONSTITUTION:Ward lines WL1, WL2, to WLm are separated from ward line drivers WD1, WD2, to WDm by separating transistors Q1, Q2, to Qm at the time of a bit line potential transition, the gate voltage of MIS nonvolatile memory transistor M21, M22, to Mmn on non-selective ward lines WL2, to WLm and the voltage of a substrate SUB are maintained at equal potential and the erroneous erasure is eliminated by short-circuiting the ward lines WL1, WL2, to WLm and the substrate SUB with short-circuiting transistors P1, P2, to Pm.</p> |
