发明名称 |
FLOATING POINT DATA PROCESSOR |
摘要 |
<p>FLOATING POINT DATA PROCESSOR A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle.</p> |
申请公布号 |
CA1096048(A) |
申请公布日期 |
1981.02.17 |
申请号 |
CA19770273438 |
申请日期 |
1977.03.08 |
申请人 |
FLOATING POINT SYSTEMS, INC. |
发明人 |
O'LEARY, GEORGE P. |
分类号 |
G06F7/00;G06F7/50;G06F7/52;G06F7/57;G06F7/76;G06F9/38;(IPC1-7):06F7/38 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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