| 摘要 |
PURPOSE:To cope with a high speed data communication, by providing a direct memory access circuit receiving a received data of series-parallel conversion, and a counter counting the number of received data received during the processing of a processor. CONSTITUTION:The processor 1 sets an initial memory address to a memory address register in a direct memory access DMA circuit 10 at the start of the receiving operation. Further, the circuit 10 reads a received data from a series- parallel conversion circuit 4 and adds the memory address register by one at every write to a memory 2. Then, a binary counter 12 counts a DMA request signal inputted from a DMA request signal line 11. Moreover, an interrupting signal is outputted to an interruption signal line 5 connected to the processor 1 from the counter 12 when the counted value of the counter 12 is >=1. Thus, when the circuit 10 performs DMA transfer of the received data, the counter 12 is added by 1 and the interrupting signal is outputted to the processor 1 and the signal is kept until the value of the counter 12 is read. |
