| 摘要 |
PURPOSE:To produce easily a gate signal of the address information which is accurate in terms of timing by using a counter to set a gate period. CONSTITUTION:The diveo signal obtained drom a signal source 1 and to be recorded to a VTR undergoes a synchronizing separation 2 for extraction of a composite synchronizing signal. The synchronizing signal is first supplied to a mono-multi 3 and triggered at the initiation of a horizontal synchronizing signal to deliver a signal having fall to be used as a clock input of a counter 4. While the composite synchronizing signal is extracted only for its vertical synchronizing signal part through an LPF5 and supplied to a mono-multi 7 after the waveform shaping performed through a Schmitt inverter 6. The output of the mono- multi 7 is supplied to a mono-multi 8, and the output of the mono-multi 8 is used as a clear input of the counter 4. The synchronizing signal is also supplied to a mono-multi 9. The mono-multi 9 is triggered at the termination of the horizontal synchronizing signal and has a rise to output an H gate signal which is kept at a high level for a period needed for record of the address information.
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