| 摘要 |
An invalidation arrangement (30) is provided to invalidate information stored during cyclically-occurring predetermined periods of time in a main memory (1) to which read addressing circuits (15), write addressing circuits (13) and a read-write control circuit (9) are connected. This arrangement is formed by an invalidation rate generator (35) producing signals whose period corresponds to the said certain period of time, two invalidation memories (37 and 38) whose addressing inputs are coupled to the read and write addressing circuits, a write circuit (45, 46) associated with the read-write control circuit for writing an up-dating signal into the two invalidation memories at the same time the main memory is written in, an erasing circuit (50-35-52-45-46) controlled by the invalidation generator for alternately writing an erase signal into the two invalidation memories after the predetermined period of time, and an erase signal coincidence circuit (55) connected to the outputs of the invalidation memories for controlling an invalidation circuit (60) connected to the output of the main memory.
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