发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To improve the static electricity breakdown withstand voltage by a method wherein, in an EPROM, a MISFET for clamping a static electricity breakdown preventing circuit is composed of a FET with the same constitution as that of source or drain region of FET for memory cell. CONSTITUTION:A FET Qm to be a memory cell of EPROM is composed of the first gate insulating film 4, floating gate electrode 5, the second insulating film 6, a control gate electrode 7 and an N<+> type semiconductor region 10 used as a source region or a drain region. Likewise, a MISFET Qn comprises an inner (peripheral) circuit while MISFET Qc for clamping a static electricity breakdown preventing circuit is composed of the gate insulating film 4, the gate electrode 5 and the semiconductor region 10 in the high impurity concentration at the same level as that of FET Qn used as the source region or the drain region. In such a constitution, the thermal and electric field breakdown can be prevented from occurring at the PN junction of semiconductor region 10 with a semiconductor substrate 1.
申请公布号 JPS62169470(A) 申请公布日期 1987.07.25
申请号 JP19860010071 申请日期 1986.01.22
申请人 HITACHI LTD 发明人 KURODA KENICHI
分类号 H01L27/112;G11C17/00;H01L21/8246;H01L21/8247;H01L27/02;H01L27/10;H01L27/105;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L27/112
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