| 摘要 |
PURPOSE:To avoid troublesome change of lots of setting pins for changeover by switching the transmission system and the transmission speed under the control of a CPU. CONSTITUTION:In case of transmission of data by synchronizing system, a CPU 10 sets an output port P1 to '1' and sets an output port P2 to '0'. A programmable timer counter 18 counts a clock pulse from an oscillation circuit 17 and outputs a pulse signal synchronously with a transmission data TxD from a counter output OUT1. In sending a data by the asynchronizing system, the CPU 10 sets both the output ports P1, P2 to '1'. In opening a NAND gate 24, a pulse signal is given from one output OUT 0 of the programmable timer counter 18 to a transmission controller 11 via NAND gates 24, 25, 30 and 32.
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