发明名称 ERROR DETECTION SYSTEM
摘要 PURPOSE:To shorten a detection time at the same error rate by performing error detection by using stuff indication bits. CONSTITUTION:Pattern generating circuits 102 and 103 generate patterns 112 and 113 corresponding to the presence and absence of stuff. When a pattern 111 detected by a stuff indication pattern detecting circuit 101 is correct, either of comparators 104 and 105 outputs dissidence information 114 or 116, so the output of the comparator which outputs the dissidence information is inhibited by a trailing-stage inhibiting circuit 106 or 107 and neither of pieces of dissidence information 118 and 119 is inputted to pulse generating circuit 108 and 109, so that error pulses 120 and 121 are not generated. When the detected pattern 111 is not correct, both comparators 104 and 105 judge dissidence and error pulses 120 and 121 are inputted to an OR circuit 110 without being inhibited by the inhibiting circuits 106 and 107, so that an error pulse 122 is outputted.
申请公布号 JPS63107241(A) 申请公布日期 1988.05.12
申请号 JP19860253046 申请日期 1986.10.23
申请人 NEC CORP 发明人 ONO SHO;HAYASHI KUNIYASU
分类号 H04L1/00;H04J3/14 主分类号 H04L1/00
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