BIT PHASE SYNCHRONIZING CIRCUIT

摘要

PURPOSE:To attain the operation of a spatial split type switch with a common clock by constituting the circuit with a clock frequency divider circuit and an elastic storage of conventional constitution so as to allow a data to take over a clock having a speed of a multiple of N and independent bit phase. CONSTITUTION:A clock frequency divider circuit 2 receives a 2nd clock 3 and outputs the clock while dividing the frequency to 1/N. A clock 1 and a data D synchronously with the clock are inputted to an elastic storage ES. With a clock 3 having a frequency at a multiple of N of the frequency of the clock 1 and independent bit phase received to the circuit 2, the frequency divider circuit 2 divides the clock frequency into the frequency the same as the frequency (1/N) of the clock 1 and the resulting signal is inputted to a terminal C2 of the elastic storage ES as the clock 2. A data synchronously with the clock 2 is outputted from a terminal Q of the elastic storage ES. The output data is naturally synchronously with the clock 3.