| 摘要 |
<p>PURPOSE:To make the circuit scale small by applying timing control to a delay circuit in response to the result of frame synchronizing pattern collation of an input data subject to parallel conversion so as to control a timing of an S/P conversion circuit. CONSTITUTION:A high speed digital signal is separated into four systems by an S/P conversion circuit 1, and inputted to a synchronizing pattern detection circuit 3 provided with shift registers 8-11. Resulting signals P1-P4 of pattern collation by the circuit 3 are inputted to a synchronizing position detection circuit 4, which gives control data S1, S2 to a delay circuit 6 to change the connection of a selector 7. Through the constitution above, the output timing of the S/P converter is controlled to realize the high speed synchronizing circuit with a small scale.</p> |
