| 摘要 |
PURPOSE:To optionally set a phase difference from a reference signal variably in the phase shift of a clock signal or the like relating to the relevant reference signal. CONSTITUTION:A phase difference signal inputted to a complete integration circuit 9 is multiplied with a prescribed constant by a 2nd multiplier and its output and an output resulting from delaying an output of a delay device 13 through a 3rd adder 11 for a prescribed time are added by the adder 11. The output of the circuit 9 and the output of the 1st multiplier 6 are added by an adder 7, the result is D/A-converted by a D/A converter 13 and an analog converted control signal 14 is outputted. |
