发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit for performing a normally stable operation at the time of a high speed operation by automatically switching to a phase comparator for normal in the case that a PLL is unlocked at the time of a high speed mode and to the phase comparator for high speed when the PLL is locked again. SOLUTION: This PLL circuit is provided with the phase comparator 1 for normal and the phase comparator 2 for high speed, and is constituted of a phase comparator switching circuit 7 for automatically switching output from the two phase comparators depending on whether or not the PLL is locked in the case of the high speed mode, a charge pump 5 for deciding the input/ output amount of a current, a low-pass filter 6 for converting the current to a voltage and a voltage controlled oscillator 3.
申请公布号 JPH11205132(A) 申请公布日期 1999.07.30
申请号 JP19980003668 申请日期 1998.01.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIMOI YASUYOSHI;FUJIMORI YOSHIHISA
分类号 H03L7/087;H03L7/10 主分类号 H03L7/087
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