| 摘要 |
An integrated circuit is disclosed that includes a first signal line adjacent to a second signal line. A first latch is coupled between the first and second signal line. The first latch includes a first transistor having a first current electrode coupled to the first signal line and a control electrode coupled to the second control line and a second transistor having a first current electrode coupled to the second signal line and a control electrode coupled to the first signal line. The first signal line typically runs substantially parallel to the second signal line. A signal generator circuit may be coupled to a first end of the first and second signal lines and a receiver circuit may be coupled to a second end of the first and second signal line. The first latch may be coupled closer to the second end of the first and second signal lines than the first end of the first and second signal lines. In one embodiment, the signal generator circuit comprises a precharge circuit that precharges the first and second signal lines to a predetermined voltage such as a low state or a high state. The circuit may include additional signal lines and additional latches where a latch is coupled between each pair of adjacent signal lines. In an embodiment in which the latch transistors are NMOS transistors, the second current electrodes of each of the transistors is coupled to a ground node. The signal lines may comprise the word lines of a semiconductor memory. |
