| 摘要 |
PROBLEM TO BE SOLVED: To obtain a method for design change of a semiconductor which shortens the design period without return of the design. SOLUTION: The method is provided with a place and route step 102 for performing the routing of layout and logic optimization by using a netlist 101 to generate a netlist 103 and layout 104, an ECO(engineering change order) step 105 for performing a logic change on design for the netlist 101 to generate a netlist 106, an ECO format verification step 107 for changing the netlist 103 so as to become logically equivalent with the netlist 106 to generate a netlist 108, and an ECO step 109 for changing layout 104 so as to be equal to the netlist 108 to generate a layout 110.
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