| 摘要 |
A graphics controller for high speed transmission for memory read commands. The graphics controller chip includes a logic circuit coupled to a first memory. The logic circuit is adapted to respond to a first issued command from a CPU by determining whether the condition that a first command is a memory read command is true. If the condition is true, the logic circuit causes the graphics controller chip to store the first command in the first memory and to begin carrying out the first command. If the condition is false, the logic circuit causes the graphics controller chip to check whether the graphics controller chip is ready to carry out the first command. If the graphics controller chip is not ready to carry out the first command, the logic circuit causes the graphics controller chip to continue checking and to send a signal to the CPU indicating that the graphics controller chip is ready to receive a second command from the CPU.
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