发明名称 |
Interconnectable nanoscale computational stages |
摘要 |
Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the configurable logic array. Each nanoscale computational stage receives signals and passes the signals through the nanoscale logic array and to a nanoscale latch array. Signals output from the nanoscale latch array can be routed to another nanoscale computational stage or out of the computing circuit.
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申请公布号 |
US7307448(B2) |
申请公布日期 |
2007.12.11 |
申请号 |
US20050136935 |
申请日期 |
2005.05.24 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
SNIDER GREGORY S.;KUEKES PHILIP J. |
分类号 |
H03K19/173 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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