发明名称 Semiconductor package suppressing a warpage and wire open defects and manufacturing method thereof
摘要 <p>Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a circuit substrate having a slit inside the circuit substrate, a semiconductor chip formed on an upper surface of the circuit substrate, a wire connecting the semiconductor chip and the circuit substrate through the slit, and a sealant partially covering the wire. According to the semiconductor package, by forming the sealant covering only a part of the wire, wire severing and warping of the semiconductor package can be prevented. In addition, the thickness of a stacked type semiconductor package can be reduced.</p>
申请公布号 KR100825784(B1) 申请公布日期 2008.04.28
申请号 KR20060101561 申请日期 2006.10.18
申请人 发明人
分类号 H01L21/60;H01L23/48 主分类号 H01L21/60
代理机构 代理人
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