Display device comprising dual transistor with LDD regions overlapping the gate electrodes and one of a source electrode and a drain electrode of first transistor is electrically connected to the second gate electrode

摘要

The present invention provides a highly controllable device for exposure from the back side and an exposure method, and also provides a method of manufacturing a semiconductor device using the same. The present invention involves exposure with the use of the back side exposure device of which a reflecting means is disposed on the front side of a substrate, apart from a photosensitive thin film surface by a distance X (X=0.1 μm to 1000 μm), and formation of a photosensitive thin film pattern in a self alignment manner, with good controllability, at a position a distance Y away from the end of a pattern. The invention fabricates a TFT using that method.

主权项

1. A display device comprising:
a first wiring; a second wiring; a first transistor comprising a first gate electrode, a gate insulating film over the first gate electrode, and a first semiconductor layer comprising a first LDD region over the gate insulating film; a second transistor comprising a second gate electrode, the gate insulating film over the second gate electrode, and a second semiconductor layer comprising a second LDD region over the gate insulating film; an insulating film over the first transistor and the second transistor; a first electrode over the insulating film; a light emitting layer over the first electrode; and a second electrode over the light emitting layer, wherein a part of the first LDD region overlaps with the first gate electrode, wherein a part of the second LDD region overlaps with the second gate electrode, wherein the first gate electrode is electrically connected to the first wiring, wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the second wiring, wherein the first gate electrode is formed in a different layer from the first wiring, wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the second gate electrode, and wherein the first wiring is parallel to the second wiring.