| 摘要 |
PURPOSE:To facilitate the increase of a capacity and to minimize the change of the existing hardware by parallely operating a set of a cache memory (buffer memory), a directory, and a comparator with an arbitrary number. CONSTITUTION:A cache memory 11, a directory 12, and a comparator 14 are constituted one set. A cache memory 15, a directory 16, and a comparator 17 are constituted another set. These sets are parallely connected to an address register 13. The hit from comparators 14 and 17 of each pair is in correspondence with pointer data from a pointer register 20 in AND circuits 21 and 22, used as the hit output with the result arranged in an OR circuit 18, also used as a chip select signal for each corresponding cache memory 11 and 15. Even when the comparators 14 and 17 of plural sets output the hit simultaneously, the one which is permitted by the AND circuits 21 and 22 is made effective. |
