| 摘要 |
1,243,433. Selective signalling. TEXACO DEVELOPMENT CORP. 24 June, 1969 [17 July, 1968], No. 31726/69. Heading G4H. [Also in Divisions G1 and H3] In a pulse height digitizer an input .pulse 10, Fig. 1, if it is above a minimum level 14, is inverted 18 and amplified A1 to establish a potential on a hold capacitor corresponding to its peak height, which potential is amplified 20 and digitized by a conventional self-balancing closed loop 24, 26, 28, 30 At the end of the conversion a control trigger 16 is turned off which closes both a switch S2-to discharge the hold capacitor 22- and a switch S3-to allow a balance capacitor C2 to charge to the output level of the digitizer comparator (which theoretically should be zero) so as to act as a compensatory bias for the next digitizing cycle. The amplifier A1, a following amplifier 20 and a feed-back loop to a summing junction + (details in Fig. 2, not shown) form an operational amplifier of gain -1. In operation when a pulse height is to be sampled a switch S1 is closed and switches S2 and S3 are opened (S2 details Fig. 3, not shown). The potential on the hold capacitor 22 then follows the leading edge of the pulse and remains at its peak-reverse current flow being prevented by a diode D1-and at the end of the pulse the switch S1 responds to the output of amplifier Al going positive and opens, thereby preventing the entry of subsequent pulses until the switch is closed by control means not described. |
