A DIGITAL MEMORY SHIFT REGISTER INCORPORATING TARGET DATA AVERAGING THROUGH A DIGITAL SMOOTHING LOOP

摘要

A digital memory shift register subsystem having a series of eight 1,024 bit shift register modules coupled together to create serial storage of 512 16-bit digital words of target information through a full adder and a full subtractor, a part of the digital memorized target information being taken as an output from the memory shift register prior to its end bit and conducted to a supplemental shift register and multiplexer combination circuit to add in and subtract from the target information digital information in the memory shift register by this recirculation to provide outputs to a display and other circuits of a sonar receiver.