| 摘要 |
A read-only memory as MOS device is disclosed, operating with a two phase clock, decoder and decoder drivers using minimum size components. The memory cells are arranged on intersections of gate platings-conductive zone columns. The gate platings are driven by serial connected decoders during one phase, and discharged in the other phase during which column nodes are charged, selectively discharged during first phases in dependence upon further decoder circuitry.
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