发明名称 DIGITAL PHASE SYNCHRONOUS CIRCUIT
摘要 PURPOSE:To secure the synchronization whether or not the input signal is the intermittent signal by increasing or decreasing the oscillation frequency based on the command delivered according to the code of the input signal and at the input time point of the code identification timing signal. CONSTITUTION:When input signal S1 featuring the waveform distorted by the noise and the like is supplied to terminal 1, the sampling is given to S1 at sampler 11 and with pulse S6 to deliver signal S7. Digital filter 12 receives S7 and delivers signal S8 which shows the timing signal component of S1. On the other hand, the output of oscillator OSC is divided through divider circuits 23 and 7 to produce signal S10. Then S10 is applied to code identification circuit 14 to check the output of filter 12. As signal S6 is produced by dividing 15 the output of OSC, signal S6 and accordingly signal S8 are synchronized with signal S10. Circuit 14 delivers at the time point of occurrence of S10 signal S11 to increase the oscillation frequency of OSC and signal S'11 to decrease the oscillation frequency in case signal S8 is positive and negative respectively. Thus the synchronization can be obtained between the oscillation phase of OSC and the zero point of the timing signal.
申请公布号 JPS5520074(A) 申请公布日期 1980.02.13
申请号 JP19780093503 申请日期 1978.07.31
申请人 FUJITSU LTD 发明人 HAYASHI TATSUKI;MURANO KAZUO;UMIGAMI SHIGEYUKI;ITOU YASUKAZU;AMANO FUMIO
分类号 H04L7/033 主分类号 H04L7/033
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