发明名称 PARALLEL DATA TRANSMISSION SYSTEM
摘要 PURPOSE:To transmit high-speed data through a low-speed data transmission line by separating the high-speed data into plural low-speed data and transmitting them in parallel together with added frame synchronizing signals, and synthesizing them into the high-speed data on a reception side. CONSTITUTION:At a transmitting data terminal station 1, high-speed data 2 is inputted to a separating circuit 3 for separating the input data, bit by bit, into plural data cyclically. In the figure, the high-speed data 2 is separated into five low-speed strings 5-9. Those low-speed data strings 5-9 are given frame synchronizing signals by a frame appending circuit 10 and then transmitted to a receiving data terminal station 12 through low-speed transmission lines 11-1- 11-5. The separated data received by memory circuits 13-1-13-5 through the low-speed transmission lines are inputted through frame detecting circuits 14-1- 14-5 to a synthesizing circuit 16, which reconstitutes the original high-speed data 2.
申请公布号 JPS5836052(A) 申请公布日期 1983.03.02
申请号 JP19810133699 申请日期 1981.08.26
申请人 FUJITSU KK 发明人 HIRAOKA MAKOTO;HANABATAKE TOSHIO
分类号 H04L25/02;H04J3/06;H04L25/14 主分类号 H04L25/02
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