| 摘要 |
The present invention provides fractional frequency dividers using inexpensive digital components in a relatively simple circuit for producing a substantially spectrally pure clock signal, free of significant time or phase jitter. The synthesizer and method include a reference frequency register for providing a frequency set value, which frequency set value is proportional to the desired frequency, a summer, having a finite storage capacity, for adding the frequency set value to a stored summed value to form a new summed value which new summed value is stored as the summed value. A carry signal is generated when the new summed value exceeds the finite storage capacity. In that event, only that portion of the new summed value in excess of the finite storage capacity is stored as the summed value. A variable time delay clock generator generates the desired clock signal so that each pulse is generated in response to the carry signal and delayed by a delay period equal to the period of a master clock signal minus a fraction of the master period. This fraction is relative to both the summed value and the frequency set value. In the preferred embodiment the frequency set value is equal to the desired frequency divided by the master frequency times a constant, which constant is related to the finite storage capacity and the fraction is equal to the summed value divided by the frequency set value.
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