发明名称
摘要 PURPOSE:To display each line in a prescribed correct position, by storing digital signal data of a vertical deflecting signal of every line in a digital memory and reading data for every line at the display time. CONSTITUTION:Deflection data for correct vertical deflection of each of plural lines is stored preliminarily in a digital memory 50. In case of the deflection for actual picture display, a switch 55 is set to the R side to set the memory 50 to the read state, and a switch circuit 56 is connected to the side of an address counter 51. The counter 51 is reset by a vertical synchronizing signal V and counts a horizontal synchronizing signal H hereafter. That is, address data corresponding to each line is outputted from the counter 51 to address the memory 50. A digital signal of the line corresponding to address data from this counter 51 is outputted and is converted to an analog signal by a D/A converter 52 to obtain a deflection signal. Thus, a desired deflected waveform is obtained.
申请公布号 JPS616587(B2) 申请公布日期 1986.02.27
申请号 JP19810205469 申请日期 1981.12.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MASUDA MITSUYA;INOHARA SHIZUO;TAKUHARA SADAHIRO;UEDA MINORU;YAMAMOTO HIROSUKE;YASUMOTO YOSHIO
分类号 H04N5/68;G09G1/20;H04N5/66 主分类号 H04N5/68
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